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Título del libro: 2015 Ieee Nuclear Science Symposium And Medical Imaging Conference, Nss/mic 2015
Título del capítulo: Extraction procedure for MOS structure fringing gate capacitance components

Autores UNAM:
JULIO CESAR TINOCO MAGAÑA;
Autores externos:

Idioma:
Inglés
Año de publicación:
2016
Palabras clave:

Extraction; Microelectronics; Reconfigurable hardware; Capacitance extraction; Extraction procedure; Fringing capacitance; Future technologies; Gate capacitance; Microelectronics industry; MOS technology; Nanometric ranges; Capacitance


Resumen:

The microelectronics industry has progressed astonishingly along several decades, thanks to the MOS transistor shrinkage. However, the parasitic gate capacitance becomes an important concern for device behavior optimization in the nanometric range. The fringing parasitic gate capacitance exhibits weaker channel length dependence than the intrinsic counterpart. For this reason, the relative weight of the parasitic gate capacitance will be more significant for future technology nodes. In this contribution, an extraction procedure to determine the main fringing components of a simple MOS structure is presented. Numerical simulations were used to validate the presented methodology. Finally, results indicate that for sub-25 nm gate electrode length, normalized total fringing capacitance associated to the transistor width is greater than the intrinsic counterpart. © 2015 IEEE.


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